-----------------------------------------------------------------------------
-- This file is a part of the ARM9 VHDL model with architecture ARMv4
-- Copyright (C) 2001 Escuela Superior de Ingenieros (ESI) Sevilla
-----------------------------------------------------------------------------
-- Entity: testbench
-- File: testprot.vhd
-- Author: Francisco Javier Jurado Carmona
-- Tutor: Jonathan Noel Tombs
-- Description: PROTOTIPO: test bench (only for simulation)
------------------------------------------------------------------------------
-- Version control:
-- 20-10-2001: First implemetation
------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE STD.TEXTIO.ALL;
USE IEEE.std_logic_textio.all;
use work.ARM8.all;
ENTITY testbench IS
END ENTITY;
ARCHITECTURE comp of testbench IS
COMPONENT prototipo
port ( clk: in std_logic;
nReset: in std_logic;
salida: out STD_LOGIC_VECTOR (11 DOWNTO 0) );
END COMPONENT;
signal clk,nreset: std_logic:= '0';
signal captura,pcaptura,salida: std_logic_vector (11 downto 0);
FILE proto: TEXT IS OUT "prototip.dat";
begin
U1: prototipo
PORT MAP (clk,nreset,salida);
clk<=NOT clk after 50 ns;
nreset <= '0' after 5 ns, '1' after 55 ns;
test_driver: PROCESS (clk,salida)
VARIABLE linea: LINE;
VARIABLE str0: STRING (1 TO 78) :=
"--------------------------------- NUEVO CICLO --------------------------------";
VARIABLE str1: STRING (1 TO 8) := "salida: ";
VARIABLE str16: STRING (1 TO 12) := " R15(PC) ";
BEGIN
pcaptura<=salida;
IF (clk='0' and clk'event) THEN
if (salida/=captura) then
write (linea, str0);
WRITELINE (proto,linea);
write (linea, str1);
write (linea, SALIDA);
write (linea,str16);
hwrite (linea,DEBUG_15);
WRITELINE (proto,linea);
end if;
end if;
end process;
synch: process (clk, nreset)
begin
if nreset='0' then
captura<=(others=>'0');
elsif clk'event and clk='1' then
captura<=pcaptura;
end if;
end process;
end COMP;
e-REdING. Biblioteca de la Escuela Superior de Ingenieros de Sevilla.
