-----------------------------------------------------------------------------
-- This file is a part of the ARM8 VHDL model
-- Copyright (C) 2001 Escuela Superior de Ingenieros (ESI) Sevilla
-----------------------------------------------------------------------------
-- Entity: display
-- File: display.vhd
-- Author: Francisco Javier Jurado Carmona
-- Tutor: Jonathan Noel Tombs
-- Description: display interface
------------------------------------------------------------------------------
-- Version control:
-- 21-11-2001: First implemetation
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.ARM8.all;
entity display is
port (
clk: in std_logic;
nReset: in std_logic;
WData: in std_logic_vector (31 downto 0);
VAddress: in std_logic_vector (31 downto 0);
we: in std_logic;
salida: out std_logic_vector (31 downto 0)
);
end display;
architecture COMP of display is
signal Dis_Reg, pDis_Reg: std_logic_vector (31 downto 0);
begin
disp: process (we,WData,VAddress,Dis_Reg)
begin
pDis_Reg<=Dis_Reg;
if we='1' and VAddress=A_DISPLAY then
pDis_Reg<=WData;
end if;
end process;
synch: process (clk, nReset)
begin
if nReset='0' then
Dis_Reg<=(others=>'0');
elsif clk'event and clk='1' then
Dis_Reg<=pDis_Reg;
end if;
end process;
salida(31 downto 8)<=Dis_Reg(31 downto 8);
salida(7 downto 0)<=not Dis_Reg(7 downto 0);
end COMP;
e-REdING. Biblioteca de la Escuela Superior de Ingenieros de Sevilla.
