-----------------------------------------------------------------------------
-- This file is a part of the ARM9 VHDL model with architecture ARMv4
-- Copyright (C) 2002 Escuela Superior de Ingenieros (ESI) Sevilla
-----------------------------------------------------------------------------
-- Entity: mem_perso
-- File: memperso.vhd
-- Author: Francisco Javier Jurado Carmona
-- Tutor: Jonathan Noel Tombs
-- Description: personalized memory interface
------------------------------------------------------------------------------
-- Version control:
-- 21-1-2002: First implemetation
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.ARM8.all;
entity memperso is
port (
ws: in std_logic_vector (1 downto 0);
d_address: in std_logic_vector (31 downto 0);
cRdata: out std_logic_vector (31 downto 0);
cWdata: in std_logic_vector (31 downto 0);
csize: in std_logic_vector (1 downto 0);
re: in std_logic;
we: in std_logic;
VAddress: out std_logic_vector (31 downto 0);
RData: in std_logic_vector (31 downto 0);
WData: out std_logic_vector (31 downto 0);
r_enable: out std_logic;
w_enable: out std_logic;
cs0,cs1,cs2,cs3: out std_logic;
wait_state: out std_logic_vector (1 downto 0)
);
end memperso;
architecture COMP of memperso is
begin
mem: process (ws, d_address, CWdata, csize, re, we, RData)
begin
VAddress<=d_address;
WData<=cWData;
cRData<=RData;
r_enable<=re;
w_enable<=we;
wait_state<=ws;
cs0<='1'; -- memory bank 0 chip select: low level active
cs1<='1'; -- memory bank 1 chip select: low level active
cs2<='1'; -- memory bank 2 chip select: low level active
cs3<='1'; -- memory bank 3 chip select: low level active
if re='1' or (we='1' and csize="11") then
cs0<='0';
cs1<='0';
cs2<='0';
cs3<='0';
elsif we='1' then
if csize="10" and d_address(1)='0' then
cs0<='0';
cs1<='0';
elsif csize="10" and d_address(1)='1' then
cs2<='0';
cs3<='0';
elsif csize="01" then
if d_address(1 downto 0)="00" then cs0<='0';
elsif d_address(1 downto 0)="01" then cs1<='0';
elsif d_address(1 downto 0)="10" then cs2<='0';
elsif d_address(1 downto 0)="11" then cs3<='0';
end if;
end if;
end if;
end process;
end COMP;
e-REdING. Biblioteca de la Escuela Superior de Ingenieros de Sevilla.
