-----------------------------------------------------------------------------
-- This file is a part of the ARM8 VHDL model
-- Copyright (C) 2001 Escuela Superior de Ingenieros (ESI) Sevilla
-----------------------------------------------------------------------------
-- Entity: mul_a
-- File: multiply.vhd
-- Author: Francisco Javier Jurado Carmona
-- Tutor: Jonathan Noel Tombs
-- Description: an absurd entity
------------------------------------------------------------------------------
-- Version control:
-- 05-12-2001: First implemetation
-- 28-12-2001: First revision
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.ARM8.all;
entity mul_a is
port (A: IN std_logic_vector(31 downto 0);
B: IN std_logic_vector(31 downto 0);
Y: OUT std_logic_vector(63 downto 0)
);
end mul_a;
architecture comp of mul_a is
begin
Y<=unsigned(A)*unsigned(B);
end comp;
e-REdING. Biblioteca de la Escuela Superior de Ingenieros de Sevilla.
