LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY rom2 IS
PORT (
Addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Data : INOUT STD_LOGIC_VECTOR(31 downto 0));
END rom2;
ARCHITECTURE second OF rom2 IS
BEGIN
s: process(Addr)
variable vadd: integer;
BEGIN
vadd := conv_integer(Addr(29 downto 0));
CASE vadd IS
when 0 =>
Data <= X"0000006E";
when 4 =>
Data <= X"000000EE";
when 8 =>
Data <= X"000000B6";
when 12 =>
Data <= X"000000E0";
when 16 =>
Data <= X"000000EE";
when 20 =>
Data <= X"00000000";
when 24 =>
Data <= X"0000001C";
when 28 =>
Data <= X"0000007C";
when 32 =>
Data <= X"0000009E";
when 36 =>
Data <= X"000000BE";
when 40 =>
Data <= X"000000FC";
when 44 =>
Data <= X"00000061";
when 48 =>
Data <= X"00000000";
when 52 =>
Data <= X"00000000";
when 56 =>
Data <= X"00000000";
when 60 =>
Data <= X"00000000";
when 64 =>
Data <= X"00001388";
when 68 =>
Data <= X"00000060";
when others =>
-- saltar a 0
Data <= X"FFFFFFFF";
end case;
end process;
END second;
CONFIGURATION cfg_rom2 OF rom2 IS
FOR second
END FOR;
END cfg_rom2;
e-REdING. Biblioteca de la Escuela Superior de Ingenieros de Sevilla.
